Simulated Annealing Approach onto VLSI Circuit Partitioning

Authors

  • Arijit Bhattacharya Department of Computer Science, APC College, New Barrackpore, West Bengal
  • Sayantan Ghatak Department of CSE, University of Calcutta, Kolkata - 700009, West Bengal
  • Satrajit Ghosh Department of Computer Science, APC College, New Barrackpore, West Bengal
  • Rajib Das Department of CSE, University of Calcutta, Kolkata - 700009, West Bengal

DOI:

https://doi.org/10.15415/mjis.2014.22010

Keywords:

Circuit Partitioning, Intractability, Metaheuristics, Randomized search, Simulated Annealing, Partitioning in vlsi

Abstract

Decompositions of inter-connected components, to achieve modular independence, poses the major problem in VLSI circuit partitioning. This problem is intractable in nature, Solutions of these problems in computational science is possible through appropriate heuristics. Reduction of the cost that occurs due to interconnectivity between several VLSI components is referred to in this paper. Modification of results derived by classical iterative procedures with probabilistic methods is attempted. Verification has been done on ISCAS-85 benchmark circuits. The proposed design tool shows remarkable improvement results in comparison to the traditional one when applied to the standard benchmark circuits like ISCAS-85.

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References

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Published

2014-03-03

How to Cite

Arijit Bhattacharya, Sayantan Ghatak, Satrajit Ghosh, and Rajib Das. 2014. “Simulated Annealing Approach onto VLSI Circuit Partitioning”. Mathematical Journal of Interdisciplinary Sciences 2 (2):133-39. https://doi.org/10.15415/mjis.2014.22010.

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Articles